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19-2175; Rev 2; 4/10
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
General Description
The MAX1185 is a 3V, dual 10-bit analog-to-digital converter (ADC) featuring fully-differential wideband trackand-hold (T/H) inputs, driving two pipelined, nine-stage ADCs. The MAX1185 is optimized for low-power, high dynamic performance applications in imaging, instrumentation, and digital communication applications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 105mW while delivering a typical signal-tonoise ratio (SNR) of 59.5dB at an input frequency of 7.5MHz and a sampling rate of 20Msps. Digital outputs A and B are updated alternating on the rising (CHA) and falling (CHB) edge of the clock. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with singleended inputs. In addition to low operating power, the MAX1185 features a 2.8mA sleep mode as well as a 1A power-down mode to conserve power during idle periods. An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1185 features parallel, multiplexed, CMOScompatible three-state outputs. The digital output format can be set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1185 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40C to +85C) temperature range. Pin-compatible, nonmultiplexed. high-speed versions of the MAX1185 are also available. Please refer to the MAX1180 data sheet for 105Msps, the MAX1181 data sheet for 80Msps, the MAX1182 data sheet for 65Msps, the MAX1183 data sheet for 40Msps, and the MAX1184 data sheet for 20Msps.
Features
o Single 3V Operation o Excellent Dynamic Performance: 59.5dB SNR at fIN = 7.5MHz 74dB SFDR at fIN = 7.5MHz o Low Power: 35mA (Normal Operation) 2.8mA (Sleep Mode) 1A (Shutdown Mode) o 0.02dB Gain and 0.25 Phase Matching o Wide 1Vp-p Differential Analog Input Voltage Range o 400MHz, -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o Single 10-Bit Bus for Multiplexed, Digital Outputs o User-Selectable Output Format--Two's Complement or Offset Binary o 48-Pin TQFP Package with Exposed Paddle For Improved Thermal Dissipation
MAX1185
Ordering Information
PART MAX1185ECM MAX1185ECM+ TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 48 TQFP-EP* 48 TQFP-EP*
MAX1185ECM/V+ -40C to +85C 48 TQFP-EP* *EP = Exposed paddle. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Pin-Compatible Versions table at end of data sheet.
Pin Configuration
REFN REFP REFIN REFOUT D9A/B D8A/B D7A/B D6A/B D5A/B D4A/B D3A/B D2A/B
48 47 46 45 44 43 42 41 40 39 38
COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK
37
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31
D1A/B D0A/B OGND OVDD OVDD OGND A/B N.C. N.C. N.C. N.C. N.C.
Applications
High Resolution Imaging I/Q Channel Digitization Multichannel IF Sampling Instrumentation Video Application Ultrasound
MAX1185
30 29 28 27
EP
26 25
T/B
SLEEP
VDD
COM
VDD
GND
PD OE
N.C.
48 TQFP-EP
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED BY A "+" SIGN.
________________________________________________________________ Maxim Integrated Products
N.C. N.C. N.C.
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND............................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A/B-D0A/B, A/B to OGND .......................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP-EP (derate 30.4mW/C above +70C)............................................................2430mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) Lead(Pb)-free..............................................................+260C Containing lead(Pb) ....................................................+240C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 2.5V, 0.1F and 1F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS Signal-to-Noise Ratio (Note 3) Signal-to-Noise and Distortion (Note 3) Spurious-Free Dynamic Range (Note 3) SNR SINAD SFDR fINA or B = 7.5MHz, TA = +25C fINA or B = 12MHz fINA or B = 7.5MHz, TA = +25C fINA or B = 12MHz fINA or B = 7.5MHz, TA = +25C fINA or B = 12MHz 64 57 57.3 59.5 59.4 59.4 59.2 74 72 dB dB dBc fCLK CHA CHB 20 5 5.5 MHz Clock cycles VDIFF VCM RIN CIN Switched capacitor load Differential or single-ended inputs 1.0 VDD / 2 0.5 100 5 V V k pF INL DNL fIN = 7.5MHz fIN = 7.5MHz, no missing codes guaranteed 10 0.5 0.25 < 1 0 1.5 1.0 1.9 2 Bits LSB LSB % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1F and 1F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Total Harmonic Distortion (First 4 Harmonics) (Note 3) Third-Harmonic Distortion (Note 3) Intermodulation Distortion Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) REFIN Input Voltage VREFIN Positive Reference Output Voltage Negative Reference Output Voltage Differential Reference Output Voltage Range REFIN Resistance VREFP VREFN VREF RREFIN VREF = VREFP - VREFN 0.95 REFOUT TCREF 2.048 3% 60 1.25 2.048 2.012 0.988 1.024 > 50 1.10 V ppm/C mV/mA V V V V M INA+ = INA- = INB+ = INB- = COM FPBW tAD tAJ For 1.5x full-scale input SYMBOL THD HD3 IMD CONDITIONS fINA or B = 7.5MHz, TA = +25C fINA or B = 12MHz fINA or B = 7.5MHz fINA or B = 12MHz fINA or B = 11.9852MHz at -6.5dBFS, fINA or B = 12.8934MHz at -6.5dBFS (Note 4) Input at -20dBFS, differential inputs Input at -0.5dBFS, differential inputs MIN TYP -72 -71 -74 -72 -76 500 400 1 2 2 1 0.25 0.2 MAX -64 UNITS dBc dBc dBc MHz MHz ns psRMS ns % Degrees LSBRMS
MAX1185
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3
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1F and 1F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL ISOURCE ISINK ISOURCE ISINK RREFP, RREFN VREF VCOM VREFP VREFN Measured between REFP and COM, and REFN and COM VREF = VREFP - VREFN CONDITIONS MIN TYP 5 -250 250 -5 MAX UNITS mA A A mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance Differential Reference Input Voltage COM Input Voltage REFP Input Voltage REFN Input Voltage 4 1.024 10% VDD / 2 10% VCOM + VREF / 2 VCOM VREF / 2 0.8 VDD k V V V V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK Input High Threshold VIH PD, OE, SLEEP, T/B CLK Input Low Threshold VIL PD, OE, SLEEP, T/B Input Hysteresis Input Leakage Input Capacitance Output-Voltage Low Output-Voltage High Three-State Leakage Current Three-State Output Capacitance VHYST IIH IIL CIN VOL VOH ILEAK COUT ISINK = -200A ISOURCE = 200A OE = OVDD OE = OVDD 5 OVDD - 0.2 10 VIH = OVDD or VDD (CLK) VIL = 0 5 0.2 0.1 5 5
V
0.8 OVDD
0.2 VDD
V
0.2 OVDD V A pF V V A pF
DIGITAL OUTPUTS (D0A/B-D9A/B, A/B)
4
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1F and 1F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range Analog Supply Current VDD OVDD Operating, fINA or B = 7.5MHz at -0.5dBFS IVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF, fINA or B = 7.5MHz at -0.5dBFS Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA or B = 7.5MHz at -0.5dBFS Power Dissipation PDISS Sleep mode Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection Ratio TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid CLK Fall to CHB Output Data Valid Clock Rise/Fall to A/B Rise/Fall Time Output Enable Time Output Disable Time CLK Pulse Width High CLK Pulse Width Low Wake-Up Time tDOA tDOB tDA/B tENABLE tDISABLE tCH tCL tWAKE Figure 4 Figure 4 Figure 3, clock period: 50ns Figure 3, clock period: 50ns Wake-up from sleep mode (Note 6) Wake-up from shutdown (Note 6) fINA or B = 7.5MHz at -0.5dBFS fINA or B = 7.5MHz at -0.5dBFS fINA or B = 7.5MHz at -0.5dBFS Figure 3 (Note 5) Figure 3 (Note 5) 5 5 6 10 1.5 25 7.5 25 7.5 0.51 1.5 -70 0.02 0.25 0.2 8 8 ns ns ns ns ns ns ns s PSRR Offset Gain 2.7 1.7 3.0 2.5 35 2.8 1 9 100 2 105 8.4 3 0.2 0.1 45 10 150 15 3.6 3.6 50 V V mA A mA A mW W mV/V %/V SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Supply Current
IOVDD
CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching dB dB Degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. Note 2: Specifications at +25C are guaranteed by production test and < +25C are guaranteed by design and characterization. Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale input voltage range. Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB or better, if referenced to the two-tone envelope. Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 6: With REFIN driven externally, REFP, COM, and REFN are left unconnected while powered down. _______________________________________________________________________________________ 5
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
Typical Operating Characteristics
(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 20MHz, CL 10pF, TA = +25C, unless otherwise noted.)
FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 10 ANALOG INPUT FREQUENCY (MHz) HD3 HD2 fCLK = 20.0005678MHz fINA = 5.9742906MHz fINB = 7.5343935MHz AINA = -0.525dBFS
MAX1185 toc01
FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1185 toc02
FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD3 HD2 fCLK = 20.0005678MHz fINA = 7.5343935MHz fINB = 11.9852035MHz AINA = -0.489dBFS CHA
MAX1185 toc03
0 CHA
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 HD3 HD2 fCLK = 20.0005678MHz fINA = 5.9742906MHz fINB = 7.5243935MHz AINA = -0.462dBFS CHB
0
10
0
1
2
3
4
5
6
7
8
9
10
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1185 toc04
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 55 0 1 2 3 4 5 6 7 8 9 10 0 IM3 IM2 IM3 56 57 fIN2 fCLK = 20.0005678MHz fIN1 = 11.9852035MHz fIN2 = 12.8934324MHz AIN = -6.5dBFS
MAX1185 toc05
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1185 toc06
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 HD3 HD2 fCLK = 20.0005678MHz fINA = 7.5343935MHz fINB = 11.9852035MHz AINA = -0.471dBFS CHB
0
61 60 CHB 59 SNR (dB) 58 CHA
fIN1
10
5
10
15
20
25
30
35
40
45
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1185 toc07
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1185 toc08
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX1185 toc09
62
-60
80
60 SINAD (dB)
-64 CHA THD (dBc) -68
76 CHB SFDR (dBc) 72
CHB
58 CHA 56
-72
CHB
68
CHA
-76
64
54 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz)
-80 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz)
60 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz)
6
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 20MHz, CL 10pF, TA = +25C, unless otherwise noted
MAX1185
FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED
MAX1185 toc10
SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED
VIN = 100mVP-P 4 2 GAIN (dB) 0 -2 -4 -6 -8 SNR (dB)
MAX1185 toc11
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 7.53MHz)
MAX1185 toc12
6 4 2 GAIN (dB) 0 -2 -4 -6 -8 1 10 100
6
65 60 55 50 45 40 35
1000
1
10
100
1000
-20
-16
-12
-8
-4
0
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT POWER (dBFS)
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER (fIN = 7.53MHz)
MAX1185 toc13
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER (fIN = 7.53MHz)
MAX1185 toc14
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 7.53MHz)
MAX1185 toc15
65 60 55 SINAD (dB)
-55 -60 -65
90 85 80 SFDR (dBc) 75 70 65
THD (dBc)
50 45 40 35 -20 -16 -12 -8 -4 0 ANALOG INPUT POWER (dBFS)
-70 -75 -80 -85 -20 -16 -12 -8 -4 0 ANALOG INPUT POWER (dBFS)
60 55 -20 -16 -12 -8 -4 0 ANALOG INPUT POWER (dBFS)
INTEGRAL NONLINEARITY (BEST END-POINT FIT)
MAX1185 toc16
DIFFERENTIAL NONLINEARITY
MAX1185 toc17
GAIN ERROR vs. TEMPERATURE
MAX1185 toc18
0.3 0.2 0.1
0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3
0.4 0.3 GAIN ERROR (%FS) 0.2 CHB 0.1 0 -0.1 -0.2 CHA
INL (LSB)
0 -0.1 -0.2 -0.3 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
0
128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (C)
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7
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 20MHz, CL 10pF, TA = +25C, unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
MAX1185 toc19
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1185 toc20
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1185 toc21
0.2 0.1 OFFSET ERROR (%FS) 0 -0.1 -0.2 -0.3 CHA -0.4 -40 -15 10 35 60 CHB
38
38
37
36
IVDD (mA)
IVDD (mA)
36
34
35
32
34
30
33 85 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 TEMPERATURE (C)
28 -40 -15 10 35 60 85 TEMPERATURE (C)
ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1185 toc22
SNR/SINAD, -THD/SFDR vs. CLOCK DUTY CYCLE
MAX1185 toc23
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1185 toc24
0.25 OE = PD = OVDD 0.20
80 SNR/SINAD, -THD/SFDR (dB, dBc) SFDR 74
fINA/B = 7.53MHz
2.0100
2.0080 VREFOUT (V)
IVDD (A)
0.15
68 SNR
THD
2.0060
0.10
62
2.0040
0.05
56
SINAD
2.0020
0 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
50 35 40 45 50 55 60 65 70 CLOCK DUTY CYCLE (%)
2.0000 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1185 toc25
OUTPUT NOISE HISTOGRAM (DC INPUT)
63,000 56,000 49,000 64,515
MAX1185 toc26
2.014
70,000
2.010
VREOUT (V)
COUNTS
2.006
42,000 35,000 28,000 21,000
2.002
1.998
14,000 7,000 0 N-2 869 N-1 N 152 N+1 0 N+2
1.994 -40 -15 10 35 60 85 TEMPERATURE (C)
0
DIGITAL OUTPUT CODE
8
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
Pin Description
PIN 1 2, 6, 11, 14, 15 3, 7, 10, 13, 16 4 5 8 9 12 17 NAME COM VDD GND INA+ INAINBINB+ CLK T/B FUNCTION Common-Mode Voltage Input/Output. Bypass to GND with a 0.1F capacitor. Analog Supply Voltage. Bypass each supply pin to GND with a 0.1F capacitor. Analog supply accepts a 2.7V to 3.6V input range. Analog Ground Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. Converter Clock Input T/B selects the ADC digital output format. High: Two's complement. Low: Straight offset binary. Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. Power-Down Input. High: Power-down mode. Low: Normal operation. Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. Do not connect. A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to be present on the output. A/B follows the external clock signal with typically 6ns delay. Output Driver Ground Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1F capacitor. Output driver supply accepts a 1.7V to 3.6V input range. Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or channel B data.
18
SLEEP
19
PD
20 21-29 30 31, 34 32, 33 35 36 37 38 39 40
OE N.C. A/B OGND OVDD D0A/B D1A/B D2A/B D3A/B D4A/B D5A/B
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9
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
Pin Description (continued)
PIN 41 42 43 44 45 46 47 48 -- NAME D6A/B D7A/B D8A/B D9A/B REFOUT REFIN REFP REFN EP FUNCTION Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 7. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 8. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 9 (MSB). Depending on status of A/B, output data reflects channel A or channel B data. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-divider. Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 1nF capacitor. Positive Reference Input/Output. Conversion range is (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor. Negative Reference Input/Output. Conversion range is (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor. Exposed Paddle. Connect to analog ground.
Detailed Description
The MAX1185 uses a nine-stage, fully-differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. 1.5-bit (2-comparator) flash ADCs convert the held input voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two and the residues are passed along to the next pipeline stages, where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. Both input channels are sampled on the rising edge of the clock and the resulting data is multiplexed at the output. CHA data is updated on the rising edge (five clock cycles later) and CHB data is updated on the falling edge (5.5 clock cycles later) of the clock signal. The A/B indicator follows the clock signal with a typical delay time of 6ns and remains high when CHA data is updated and low when CHB data is updated.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1185 to track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA- as well as INB+ and INB- and set the common-mode voltage to midsupply (VDD / 2) for optimum performance.
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
VIN T/H x2 VOUT VIN T/H x2 VOUT
FLASH ADC 1.5 BITS
DAC
FLASH ADC 1.5 BITS
DAC
2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 STAGE 9 STAGE 1 STAGE 2 STAGE 8
2-BIT FLASH ADC STAGE 9
DIGITAL CORRECTION LOGIC T/H 10 T/H VINB OUTPUT MULTIPLEXER 10 D0A/B-D9A/B
DIGITAL CORRECTION LOGIC 10
VINA
Figure 1. Pipelined Architecture--Stage Blocks
INTERNAL BIAS S2a C1a S4a INA+ C2a S4c S1 OUT S4b C2b C1b S2b INTERNAL BIAS INTERNAL BIAS S2a C1a S4a INB+ C2a S4c S1 OUT S4b C2b C1b S2b INTERNAL BIAS S5b COM S3b OUT S5b COM COM S5a S3a HOLD TRACK HOLD TRACK CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS S3b OUT COM S5a S3a
INA-
MAX1185
INB-
Figure 2. MAX1185 T/H Amplifiers
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
Analog Inputs and Reference Configurations
The full-scale range of the MAX1185 is determined by the internally generated voltage difference between REFP (VDD / 2 + VREFIN / 4) and REFN (VDD / 2 - VREFIN / 4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD / 2), and REFN are internally buffered low-impedance outputs. The MAX1185 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10k) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes, bypass REFIN with a > 10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a > 10k resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate, external reference sources. The MAX1185 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics.
System Timing Requirements
Figure 3 shows the relationship between clock and analog input, A/B indicator, and the resulting CHA/CHB data output. CHA and CHB data are sampled on the rising edge of the clock signal. Following the rising edge of the 5th clock cycles, the digitized value of the original CHA sample is presented at the output, followed one half-clock cycle later by the digitized value of the original CHB sample. A channel selection signal (A/B indicator) allows the user to determine which output data represents which input channel. With A/B = 1, digitized data from CHA is present at the output and with A/B = 0 digitized data from CHB is present.
Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE), Channel Selection (A/B)
All digital outputs, D0A/B-D9A/B (CHA or CHB data) and A/B are TTL/CMOS logic-compatible. The output coding can be chosen to be either offset binary or two's complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two's complement output coding. The capacitive load on the digital outputs D0A/B-D9A/B should be kept as low as possible (< 15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1185, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1185, small-series resistors (e.g., 100) may be added to the digital output paths close to the MAX1185. Figure 4 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid.
Clock Input (CLK)
The MAX1185's CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: SNRdB = 20 x log10 (1 / [2 x fIN x tAJ]) where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.
Power-Down (PD) and Sleep (SLEEP) Modes
The MAX1185 offers two power-save modes--sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 2.8mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power-down. Pulling OE high forces the digital outputs into a high-impedance state.
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
tCLK tCL CLK tCH
tDOB A/B tDA/B D0A/B-D9A/B D0B D1A CHB CHA
tDOA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB
D1B
D2A
D2B
D3A
D3B
D4A
D4B
D5A
D5B
D6A
D6B
Figure 3. Timing Diagram for Multiplexed Outputs
OE
the amplifiers. The user may select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 5, a RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor.
tENABLE tDISABLE HIGH IMPEDANCE
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1185 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. In general, the MAX1185 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode.
OUTPUT D0A/B-D9A/B
HIGH IMPEDANCE
VALID DATA
Figure 4. Output Timing Diagram
Applications Information
Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a VDD / 2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed operational amplifiers that follows
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
Table 1. MAX1185 Output Codes For Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF x 511/512 VREF x 1/512 0 - VREF x 1/512 -VREF x 511/512 -VREF x 512/512 *VREF = VREFP - VREFN DIFFERENTIAL INPUT +FULL SCALE - 1LSB + 1 LSB Bipolar Zero - 1 LSB - FULL SCALE + 1 LSB - FULL SCALE STRAIGHT OFFSET BINARY T/B = 0 11 1111 1111 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 TWO'S COMPLEMENT T/B = 1 01 1111 1111 00 0000 0001 00 0000 0000 11 1111 1111 10 0000 0001 10 0000 0000
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
Grounding, Bypassing, and Board Layout
The MAX1185 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1F ceramic capacitors and a 2.2F bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channelto-channel crosstalk. Keep all signal lines short and free of 90 degree turns.
Typical QAM Demodulation Application
The most frequently used modulation technique for digital communications applications is probably the Quadrature Amplitude Modulation (QAM). Typically found in spreadspectrum based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 degree phaseshifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into it's I and Q components, essentially representing the modulation process reversed. Figure 8 displays the demodulation process performed in the analog domain, using the dual matched 3.3V, 10-bit ADC MAX1185 and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1185, the mixed down-signal components may be filtered by matched analog filters, such as Nyquist or Pulse-Shaping filters. These remove any unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
+5V
0.1F LOWPASS FILTER MAX4108 300 0.1F INA+ RIS0 50 CIN 22pF
-5V
0.1F
600 300 600 COM +5V 0.1F +5V 0.1F INPUT 0.1F MAX4108 300 0.1F MAX4108 INARIS0 50 0.1F CIN 22pF LOWPASS FILTER 600
-5V
300 -5V
300 300 +5V 600
MAX1185
0.1F LOWPASS FILTER MAX4108 300 0.1F INB+ RIS0 50 CIN 22pF
-5V
0.1F
600 300 600
+5V
0.1F +5V 0.1F 600 0.1F LOWPASS FILTER INBRIS0 50 -5V 0.1F CIN 22pF
INPUT MAX4108 300 0.1F MAX4108
-5V
300
300 300 600
Figure 5. Typical Application for Single-Ended-to-Differential Conversion
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
25 INA+ 22pF 0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F
COM
MINICIRCUITS TT1-6 25 INA22pF MAX1185 25 INB+ 22pF 0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F
MINICIRCUITS TT1-6 25 INB22pF
Figure 6. Transformer-Coupled Input Drive
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1185 are measured using the best straight-line fit method.
Dynamic Parameter Definitions
Aperture Jitter
Figure 9 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 9).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
REFP
VIN MAX4108 100
0.1F
1k RISO 50 INA+ 1k CIN 22pF COM REFN 0.1F RISO 50 INACIN 22pF REFP
100
MAX1185
VIN MAX4108 100
0.1F
1k RISO 50 INB+ 1k CIN 22pF
REFN
0.1F
RISO 50 INBCIN 22pF
100
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive
quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N-Bits): SNRdB[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
MAX2451
INA+ INA0 90
A/B
MAX1185 INB+ INB-
DSP POST PROCESSING
DOWNCONVERTER /8
CHA AND CHB DATA ALTERNATINGLY AVAILABLE ON 10-BIT, MULTIPLEXED OUTPUT BUS
Figure 8. Typical QAM Application, Using the MAX1185
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:
CLK
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
2 2 2 2 V2 + V3 + V4 + V5 THD = 20 x log10 V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range (SFDR)
T/H TRACK HOLD TRACK
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
Intermodulation Distortion (IMD)
Figure 9. T/H Aperture Timing
The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are backed off by 6.5dB from full scale.
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
Functional Diagram
VDD GND INA+ T/H INAPIPELINE ADC OGND OVDD
MAX1185
DEC
MUX
A/B
10 CLK CONTROL
INB+ T/H INB-
PIPELINE ADC
DEC
OUTPUT DRIVERS
10 D0A/B-D9A/B OE
REFERENCE
MAX1185
T/B PD SLEEP
REFOUT REFN COM REFP REFIN
Pin-Compatible Versions
PART MAX1190 MAX1180 MAX1181 MAX1182 MAX1183 MAX1186 MAX1184 MAX1185 MAX1198 MAX1197 MAX1196 MAX1195 RESOLUTION (Bits) 10 10 10 10 10 10 10 10 8 8 8 8 SPEED GRADE (Msps) 120 105 80 65 40 40 20 20 100 60 40 40 OUTPUT BUS Full duplex Full duplex Full duplex Full duplex Full duplex Half duplex Full duplex Half duplex Full duplex Full duplex Half duplex Full duplex
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 TQFP-EP PACKAGE CODE C48E-7 DOCUMENT NO. 21-0065
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Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
Revision History
REVISION NUMBER 2 REVISION DATE 4/10 DESCRIPTION Added automotive qualified part to Ordering Information PAGES CHANGED 1
MAX1185
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
(c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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